1. Field of the Invention
This invention relates generally to a comparator circuit, and in particular to, for example, a comparator circuit which is used in a comparison input stage of an analog-to-digital convertor circuit for sequentially converting analog signals to digital signals, and outputting them.
2. Description of the Related Art
Conventionally, in the fields of audio equipment and instrumentation, an analog-to-digital convertor circuit (hereinafter called an "A/D convertor circuit") is used widely to convert various analog signals such as audio signals to be recorded or reproduced into digital data for digital signal processing. There are various conversion methods in the A/D convertor circuit, and these are used in various application fields depending on accuracy and speed requirements.
In particular, when high speed operation or high accuracy is required, it is usual to use a parallel (flash) type A/D convertor circuit or a serial-parallel (subranging) type A/D convertor circuit, for which a resolution of 10 to 12 bits is required.
However, when the resolution is as low as 10 to 12 bits, voltage for the least significant bit (1 LSB) necessary for the A/D convertor circuit becomes very low (about 1 mV) so that the influence of the voltage difference AVBE between the base and the emitter of transistors constituting the comparator cannot be ignored.
Thus, an interpolation method is proposed in which a plurality of comparison outputs generated by a comparator are combined and compared to interpolatively find a comparison output between a virtual potential corresponding to the middle of the reference potential and an input signal VIN so as to reduce the number of comparators with this interpolation processing.
As one of such interpolation methods, an interpolation method is proposed in which the load resistances of a differential amplifier circuit constituting a comparator are arranged as a resistance array having a predetermined resistance ratio, to which an output voltage found as a difference voltage between the connection taps of each resistor is combined to obtain a comparison output between the virtual potential that is equally dividing the reference potential and an input signal.
However, in this case, there is a problem in that one additional differential amplifying stage becomes necessary for interpolation, and that there arises a time difference in the speed of the differential output from the difference in time constants because a plurality of differential outputs are generated by using resistors with different resistance values. Thus, this method cannot be used in a parallel type A/D convertor circuit.
On the other hand, an interpolation method not causing such time difference in the speed of differential outputs is proposed in which a collector current is divided by various current ratios and the divided collector currents are combined to obtain a comparison output between the virtual potential that results from the equal division of the reference potential and an input signal.
When a comparator which is obtained by interpolating a comparison output between the virtual potential, for example, that equally divides the reference potential by four and an input signal V.sub.IN, it becomes such an arrangement as shown in FIG. 1.
In this case, a differential input stage 1 inputs an input signal V.sub.IN and a reference potential V.sub.REF1 into a differential pair consisting of transistors Q1 and Q2 and compares them to divide the collector currents into mutually inverted signals which are a comparison between the input signal V.sub.IN and the reference potential V.sub.REF1 according to emitter area ratios of cascade connected transistors. Here, transistors Q3, Q4, Q5, Q6, Q7, Q8, and Q9, as well as Q9N, Q8N, Q7N, Q6N, Q5N, Q4N, and Q3N each set of which has an emitter area ratio of 1:2:3:4:3:2:1 are connected to the transistors Q1 and Q2.
Similarly, a differential input stage 2 inputs a reference potential V.sub.REF2 and the input signal V.sub.IN into a differential pair consisting of the transistors Q21 and Q22 and compares them to divide the collector currents, which are its comparison outputs in mutually inverted signals, according to emitter area ratios of the cascade connected transistors. Here, transistors Q23, Q24, Q25, Q26, Q27, Q28, and Q29, as well as Q29N, Q28N, Q27N, Q26N, Q25N, Q24N, and Q23N each set of which has an emitter area ratio of 1:2:3:4:3:2 are connected to the transistors Q21 and Q22.
Namely, the transistors Q6 to Q9 and Q6N to Q3N (Q26 to Q23 and Q26N to Q23N) divide the collector current into divided collector current IA4, IA3, IA2, and IA1, as well as IAN4, IAN3, IAN2, and IAN1 (IB4, IB3, IB2, and IB1, as well as IBN4, IBN3, IBN2, and IBN1) in proportion to the emitter area of each transistor.
This current dividing comparator is arranged to add a divided current generated by adjacent differential input stages so that all added values of the divided current in an non-inverted relationship are the same value, and to compare their comparison outputs.
Namely, as shown in FIG. 2, a comparison output between the reference potential V.sub.REF1 and the input signal V.sub.IN can be achieved by comparing the output potential VA1 and VB1 generated in load resistors R1 and R5 through which the divided collector current IA4 and IAN4 flow, respectively. Also, as shown in FIG. 3, a comparison output between the virtual reference potential V1 (=V.sub.REF1 +.DELTA.V/4) and the input signal V.sub.IN can be achieved by comparing an output potential VA2 generated in the load resistor R2 through which the composite collector current of the divided collector current IA3 and IB1 flows, and an output potential VB2 generated in the load resistor R6 through which the composite collector current of the divided collector current IAN3 and IBNL flows.
Similarly, as shown in FIG. 4, a comparison output between the virtual reference potential V2(=V.sub.REF1 +.DELTA.V/2) and the input signal V.sub.IN can be obtained by comparing an output potential VA3 generated in a load resistor R3 through which the composite collector current of the divided collector currents IA2 and IB2 flows, and an output potential VB3 generated in a load resistor R7 through which the composite collector current of the divided collector currents IAN2 and IBN2 flows. Also, as shown in FIG. 5, a comparison output between the virtual reference potential V3 (=V.sub.REF1 +3 .DELTA.V/4) and the input signal V.sub.IN can be obtained by comparing an output potential VA4 generated in the load resistor R4 through which the composite collector current of the divided collector currents IA1 and IB3 flows, and an output potential VB4 generated in load resistor R8 through which composite collector current of the divided collector currents IAN1 and IBN3 flows.
Then, as shown in FIG. 6, a comparison output of the input signal V.sub.IN to the reference potential V.sub.REF2 can be obtained by comparing the output potentials VA1 and VB1 generated in the load resistors R21 and R25 through which the divided collector currents IB4 and IBN4 flow, respectively.
In this way, when a result is obtained from the comparison between the virtual reference potential (V1, V2, and V3) dividing the reference potential V.sub.REF1 and V.sub.REF2 by four*, and the input signal V.sub.IN based on a result of the comparison between the comparison output which is obtained by adding two non-inverted outputs of the comparison outputs of the adjacent comparators in a certain ratio, and the comparison output which is obtained by adding two inverted outputs, it becomes necessary to have 14 transistors (Q3 to Q9 and Q3N to Q9N) with different ratios of emitter areas.
However, if it is intended to separately build the transistors in different emitter area ratios (that is, Q3:Q4:Q5:Q6:Q7:Q8:Q9=1:2:3:4:3:2:1) in the accuracy necessary for the comparator, it is necessary to parallel connect the transistors with the same emitter size in the number of ratios.
Therefore, if it is intended to perform interpolation for dividing the reference potential V.sub.REF1 and V.sub.REF2 by four by dividing the current in a predetermined ratio, 32 current dividing transistors are required for one comparator. If it is intended to perform interpolation for dividing the current of the reference potential V.sub.REF1 and V.sub.REF2 by eight, as much as 128 transistors of the same size are required for one comparator. This causes a problem in that the area of the circuit for the comparator is inevitably increased.
The principles of the serial/parallel A/D convertor will be described using FIG. 7.
This serial/parallel A/D convertor circuit is to convert an input signal V.sub.IN to digital data by dividing them into two stages of the upper and lower bits. Even in such type of serial/parallel A/D convertor, a two step parallel A/D convertor circuit 10 is mainly used when image signals are to be processed.
This A/D convertor circuit 10 generates reference voltages VU1, VU2, and VU3 corresponding to the upper two bits by a reference voltage generator circuit 11 which is constituted by serially connecting 16 reference resistors R. These three sets of reference voltage VU1, VU2, and VU3 are compared with the input signal V.sub.IN by upper comparators CU1, CU2, and CU3. The most significant bit D1 is generated by supplying their comparison outputs to an upper encoder 12.
The upper encoder 12 is arranged to generate a reference voltage for segmenting a voltage zone to which the upper two bits belong, and eight reference voltages VD1, VD2, . . . , VD8 in total for correcting redundancy provided for the upper and lower sides of the voltage zone by switching a group of switches SW based on the comparison outputs of the upper comparators CU1, CU2, and CU3.
It is arranged to compare these eight reference voltages VD1, VD2, . . . , VD8 with the input signal V.sub.IN at the lower comparators CD1, CD2, . . . , CD8, and to supply these comparison outputs to the lower encoder 13 so that the remaining three bits D2, D3, and D4 are generated.
However, when the resolution becomes as low as 10 to 12 bits, the voltage for the least significant bit (1 LSB) necessary for the A/D convertor circuit 10 becomes very low of about 1 mV so that an influence of the voltage difference .DELTA.VBE between the base and the emitter of the transistors constituting the lower comparators CD1, CD2, . . . , CD8 cannot be ignored when the number of bits is increased.
Thus, an interpolation method is being studied in which a plurality of comparison outputs generated by a comparator are combined and compared to interpolatively find a comparison output between the intermediate potential of the adjacent reference potential and an input signal V.sub.IN so as to eliminate the influence of the voltage difference .DELTA.VBE between the base and the emitter by reducing the number of comparators with this interpolation processing.
As one of such interpolation methods, an interpolation method is proposed in which load resistances of a differential amplifier circuit constituting a comparator are arranged as a resistance array. The resistance array is a plurality of resistances having a predetermined resistance ratio connected in series. The output voltage of the resistance array that is found as the difference voltage between the connection taps of each resistor is combined to obtain a comparison output between the intermediate potential dividing reference potential and an input signal.
However, in this case, there is a problem in that one additional differential amplifying stage becomes required for interpolation, and that there arises a time difference in the speed of the differential output due to the difference in time constants because a plurality of differential outputs are generated by using resistors with different resistance values. Thus, this method cannot be used in a low order comparator consisting of a serial/parallel A/D convertor circuit.